The present invention relates generally to switching of semiconductor power devices, and more specifically to selectively decreasing excessive voltage overshoot during fast turn-off of hard-switched high voltage semiconductor power devices.
There are many applications for high-speed switching of semiconductor power devices. Some applications are referred to as soft-switched (whether active or passive) and some are referred to as hard-switched. Hard-switching applications are those that turn a device OFF while current flows through the device, such as, for example, into an inductive load. One such application includes three-phase inverters for DC-AC power conversion and motor control in HEVs, PHEVs, and EVs. These inverters include three separate half-bridges having a high-side voltage switching element and a low-side voltage switching element, each with anti-parallel diodes. IGBTs and MOSFETs are two of the typical semiconductor switching devices used in this context. To decrease power losses, and improve inverter efficiency, silicon power devices are designed to switch quickly between on and off states. Switching the devices on and off introduces voltage and current transients (dV/dt and dI/dt) into the system. Faster switching decreases the IGBT/MOSFET turn-on and turn-off losses, but increases the associated dV/dt and dI/dt transients.
A typical system includes parasitic inductances and a DC link capacitance coupled to the switching element(s). Fast dI/dt transients produce voltages across the inductances, which are added to a DC link voltage. These cumulated voltages exist directly across the power device(s) which is/are switching from its “ON” state to its “OFF” state. Should the cumulated voltage become larger than the rated voltage of the device, the semiconductor material breaks down and the device is destroyed. The cumulative additional voltages are referred to as voltage overshoot (it overshoots the applied/desired voltage). Typically there is a larger overshoot during device turn-off, therefore the discussion herein focuses on the transients seen while a device is turning off. Some of the inventive ideas presented herein may be useful in various contexts for device turn on.
FIG. 1 is a block schematic diagram of a conventional three phase inverter 100 including a DC source 105, a DC link capacitance 110, three half bridges 115n, and three inductances 120n in a star-connected configuration representing a load, such as, for example, the windings of an electric motor. FIG. 1 also schematically represents various system parasitic inductances typically seen between the single phase half-bridge switching devices 115x and DC link capacitor 110. Not shown in FIG. 1 are the specific positive and negative controls for controlling the switches (e.g., gate voltages) of half-bridges 115n.
These inductances include LCAP, LBUS, and Ln (n=1, 2, 3), and, for an IGBT (LC, LE), and for a MOSFET (LD, LS). LCAP is inherent to the lead or terminal structure attaching the capacitive element to a busbar or FR4 board. LBUS includes the inductance from the busbar or FR4 board between the switching device leads and capacitor terminal structure. LC/LD includes the device lead and case inductance for the collector (IGBT) or drain (MOSFET) or and LS/LE includes the device lead and internal bond wire for the source (MOSFET) or emitter (IGBT). Ln includes a primary side referenced stator leakage inductance for each phase.
The following discussion and equations address operation of one phase (e.g., first phase leg 1201). It is assumed that the inductance of phase leg 1201, L1, is much larger than the other parasitic inductances in the system, and that DC link capacitance 110 is sufficiently large to prevent a change in the DC link bus voltage. When the gate of the upper switch device in half-bridge 1151 changes from a high to low voltage, the device begins its process of turning off. It is assumed that since L1 is large, the motor current I1 will not change during the device turn-off period. Before the upper device begins its turn-off sequence, the voltage across it equals the device's on-state voltage when carrying I1, while the lower device's voltage equals the DC link voltage. Since the lower switch device's anti-parallel diode must carry the current after the upper device turns off, which will not happen until the diode reaches its Vf threshold voltage, the upper device's terminal voltage must ramp up from its previous on-state voltage to carry the DC link voltage. After the upper device is carrying the DC link voltage, the lower device's diode ramps up in current and the upper device ramps down in current, until the upper device is fully blocking and the lower diode is fully conducting I1. The time for the current to ramp down in the upper device is a primary function of previous conducted current, I1, the system parasitic inductance, and the magnitude of the negative voltage rail. Equation (1) and (2) calculate the voltage on the collector/drain and emitter/source respectively; equation (3) depicts the voltage seen across the upper switch as of function of the DC link voltage, parasitic inductance, and change in switch current during turn-off.
                              V                      SWITCH            +                          =                              V            DClink                    -                                    (                                                                    1                    2                                    ⁢                                      L                    CAP                                                  +                                                      1                    2                                    ⁢                                      L                    BUS                                                  +                                  L                  C                                            )                        *                                          -                                  ⅆ                  I                                                            ⅆ                t                                                                        (        1        )                                          V                      SWITCH            -                          =                  0          -                                    (                                                                    1                    2                                    ⁢                                      L                    CAP                                                  +                                                      1                    2                                    ⁢                                      L                    BUS                                                  +                                  L                  C                                +                                  L                  E                                            )                        *                                          ⅆ                I                                            ⅆ                t                                              +                                    L              E                        *                                          -                                  ⅆ                  I                                                            ⅆ                t                                                                        (        2        )                                          V          SWITCH_overshoot                =                                            V                              SWITCH                +                                      -                          V                              SWITCH                -                                              =                                    (                                                L                  CAP                                +                                  L                  BUS                                +                                  2                  ⁢                                      L                    C                                                  +                                  2                  ⁢                                      L                    E                                                              )                        *                                          ⅆ                I                                            ⅆ                t                                                                        (        3        )            
Typically, in order to prevent the overshoot voltage during device turn-off from exceeding the device voltage rating, the bus voltage is maintained below the device rating plus the worse case overshoot. If a higher DC link bus voltage is required, many systems simply replace the switching device(s) with a larger rated device. For systems that desire to reduce the overshoot to safe levels, the device turn-off switching state must be slowed down. Using larger gate resistors is the simplest approach to slowing down the turn-off of a device, which is documented in many manufacturers' device datasheets.
Production electric vehicles must have the best efficiency and performance at the lowest cost and weight. Production electric vehicles rely on many very high voltage switching devices that switch as fast as possible. It is not desired to simply increase the rated sizes of the device just to address voltage overshoot concerns. It is not always the case that the voltage will overshoot, and the unused extra size capacity adds unnecessary costs, and may add some incremental extra weight which, cumulatively, is disadvantageous. Slowing down the switching state by changing gate resistance increases the device switching losses, which decreases the efficiency of the inverter and system because these solutions have the increased gate resistance in circuit all the time.
What is needed is a system and method for dynamic control of a gate drive negative voltage rail to efficiently and economically reduce excessive voltage overshoot.